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	Merge pull request #1645 from mailwl/thumb_pc
Fix thumb ADR instruction alignment
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				| @ -3955,9 +3955,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | ||||
|         if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { | ||||
|             add_inst* const inst_cream = (add_inst*)inst_base->component; | ||||
| 
 | ||||
|             u32 rn_val = RN; | ||||
|             if (inst_cream->Rn == 15) | ||||
|                 rn_val += 2 * cpu->GetInstructionSize(); | ||||
|             u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn); | ||||
| 
 | ||||
|             bool carry; | ||||
|             bool overflow; | ||||
| @ -6167,9 +6165,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | ||||
|         if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { | ||||
|             sub_inst* const inst_cream = (sub_inst*)inst_base->component; | ||||
| 
 | ||||
|             u32 rn_val = RN; | ||||
|             if (inst_cream->Rn == 15) | ||||
|                 rn_val += 2 * cpu->GetInstructionSize(); | ||||
|             u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn); | ||||
| 
 | ||||
|             bool carry; | ||||
|             bool overflow; | ||||
|  | ||||
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