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	spirv: Fix implicit lod type
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				| @ -101,6 +101,10 @@ public: | ||||
|         return Constant(U32[1], value); | ||||
|     } | ||||
| 
 | ||||
|     Id Const(f32 value) { | ||||
|         return Constant(F32[1], value); | ||||
|     } | ||||
| 
 | ||||
|     Id Const(u32 element_1, u32 element_2) { | ||||
|         return ConstantComposite(U32[2], Const(element_1), Const(element_2)); | ||||
|     } | ||||
|  | ||||
| @ -320,7 +320,7 @@ Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& | ||||
|         // We can't use implicit lods on non-fragment stages on SPIR-V. Maxwell hardware behaves as
 | ||||
|         // if the lod was explicitly zero.  This may change on Turing with implicit compute
 | ||||
|         // derivatives
 | ||||
|         const Id lod{ctx.Const(0)}; | ||||
|         const Id lod{ctx.Const(0.0f)}; | ||||
|         const ImageOperands operands(ctx, false, true, info.has_lod_clamp != 0, lod, offset); | ||||
|         return Emit(&EmitContext::OpImageSparseSampleExplicitLod, | ||||
|                     &EmitContext::OpImageSampleExplicitLod, ctx, inst, ctx.F32[4], | ||||
|  | ||||
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